Texas Instruments LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input LMK00101BEVAL/NOP LMK00101BEVAL/NOPB Scheda Tecnica

Codici prodotto

LMK00101BEVAL/NOPB

User’s Guide

March 2012

LMK00101 User’s Guide

SNLU098

INTRODUCTION ......................................................................................................... 2

QUICK START ............................................................................................................ 2

SIGNAL PATH AND CONTROL SWITCHES ............................................................. 4

POWER SUPPLIES ..................................................................................................... 4

CLOCK INPUTS .......................................................................................................... 4

CLOCK OUTPUTS ...................................................................................................... 5

SCHEMATICS .............................................................................................................. 6

PCB LAYOUT ............................................................................................................... 8

BILL OF MATERIALS ................................................................................................ 10

EVALUATION BOARD/KIT/MODULE (EVM).................................................................. 16

LIST OF FIGURES

Figure 1: LMK00101 Quick Start Setup ........................................................................................................................ 2

Figure 2: Schematic Sheet 1 ......................................................................................................................................... 6

Figure 3: Schematic Sheet 2 ......................................................................................................................................... 7

Figure 4: PCB Top ........................................................................................................................................................ 8

Figure 5: Bottom Side (Layer Inverted, Not to Scale) ................................................................................................... 9

LIST OF TABLES

Table 1: Part Description .............................................................................................................................................. 2

Table 2: Default Clock Output Modes / Interfaces ........................................................................................................ 3

Table 3. Input Selection (0=SW OFF, 1=SW ON) ........................................................................................................ 3

Table 4: Power Supply Configuration ........................................................................................................................... 4

Table 5: Bill of Materials .............................................................................................................................................. 10