Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 Scheda Tecnica
Codici prodotto
TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
Table 6-7. XCLKIN Timing Requirements - PLL Enabled
(1)
MIN
MAX
UNIT
t
f(XCI)
Fall time, XCLKIN
6
ns
t
r(XCI)
Rise time, XCLKIN
6
ns
t
w(XCL)
Pulse duration, XCLKIN low as a percentage of t
c(XCI)
45
55
%
t
w(XCH)
Pulse duration, XCLKIN high as a percentage of t
c(XCI)
45
55
%
(1)
The possible USB PLL configuration modes are shown in
and
.
Table 6-8. XCLKIN Timing Requirements - PLL Disabled
MIN
MAX
UNIT
t
f(XCI)
Fall time, XCLKIN
Up to 20 MHz
6
ns
20 MHz to 100 MHz
2
t
r(XCI)
Rise time, XCLKIN
Up to 20 MHz
6
ns
20 MHz to 100 MHz
2
t
w(XCL)
Pulse duration, XCLKIN low as a percentage of t
c(XCI)
45
55
%
t
w(XCH)
Pulse duration, XCLKIN high as a percentage of t
c(XCI)
45
55
%
Table 6-9. PLL Lock Times
MIN
NOM
MAX
UNIT
input clock
t
(PLL)
Lock time, Main PLL (X1, from external oscillator)
2000
(1)
cycles
input clock
t
(USB)
Lock time, USB PLL (XCLKIN, from external oscillator)
2000
(1)
cycles
(1)
For example, if the input clock to the PLL is 10 MHz, then the PLL lock time is 100 ns x 2000 = 200 µs.
6.4.2
Internal Clock Frequencies
provides the clock frequencies for the internal clocks of the F28M36x devices.
Table 6-10. Internal Clock Frequencies (150-MHz Devices)
MIN
NOM
MAX
UNIT
f
(USB)
Frequency, USBPLLCLK
60
MHz
f
(PLL)
Frequency, PLLSYSCLK
2
150
MHz
f
(OCK)
Frequency, OSCCLK
2
100
MHz
f
(M3C)
Frequency, M3SSCLK
2
100
(1)
MHz
f
(ADC)
Frequency, ASYSCLK
2
37.5
MHz
f
(SYS)
Frequency, C28SYSCLK
2
150
(1)
MHz
f
(HSP)
Frequency, C28HSPCLK
2
150
(1)
MHz
f
(LSP)
Frequency, C28LSPCLK
(2)
2
37.5
(3)
150
(1)
MHz
f
(10M)
Frequency, 10MHZCLK
10
MHz
f
(32K)
Frequency, 32KHZCLK
32
kHz
(1)
An integer divide ratio must be maintained between the C28x and Cortex-M3 clock frequencies. For example, when the C28x is
configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 will be 75 MHz. See
configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 will be 75 MHz. See
and
to see the internal clocks and clock divider options.
(2)
Lower LSPCLK will reduce device power consumption.
(3)
This is the default reset value if C28SYSCLK = 150 MHz.
Copyright © 2012–2014, Texas Instruments Incorporated
Electrical Specifications
133
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