Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Scheda Tecnica
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DK-TM4C129X
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences. If a full POK-POR is initiated, the POR bit in the RESC
register is set and all other bits are cleared. If the
their state across multiple reset sequences. If a full POK-POR is initiated, the POR bit in the RESC
register is set and all other bits are cleared. If the
WDOGn
,
BOR
or
EXTRES
configuration fields are
set to 0x3 in the RESBEHAVCTL register and a simulated POR is initiated, the cause of the reset
is reflected in the RESC register. A reset caused by a Hibernation wake event is also registered in
RESC and the specific wake event can be found by reading the Hibernation Raw Interrupt Status
(HIBRIS) register.
is reflected in the RESC register. A reset caused by a Hibernation wake event is also registered in
RESC and the specific wake event can be found by reading the Hibernation Raw Interrupt Status
(HIBRIS) register.
Note:
The Reset Cause (RESC) register identifies if the Hibernation Module was a cause of a
reset if the
reset if the
HIB
bit is set. If the V
DD
supply drops below the Power-On Reset threshold after
being above the threshold for 1-2 hibernate clock cycles (typical 30 to 60 µS), the RESC
register does not show the Hibernation Module as a reset cause. Software may determine
if the Hibernation module is configured and a wake-up source has triggered by reading the
Hibernation Control (HIBCTL) register and the Hibernation Raw Interrupt Status (HIBRIS)
register.
register does not show the Hibernation Module as a reset cause. Software may determine
if the Hibernation module is configured and a wake-up source has triggered by reading the
Hibernation Control (HIBCTL) register and the Hibernation Raw Interrupt Status (HIBRIS)
register.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type RW, reset 0x0000.0002
Offset 0x05C
Type RW, reset 0x0000.0002
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MOSCFAIL
reserved
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EXT
POR
BOR
WDT0
SW
WDT1
HIB
reserved
HSSR
reserved
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RW
RO
RO
RO
Type
0
1
0
0
0
0
0
0
0
0
0
0
-
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000
RO
reserved
31:17
MOSC Failure Reset
Writing a 0 to this bit clears it.
Description
Value
When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
0
When read, this bit indicates that the MOSC circuit was enabled
for clock validation and failed while the
for clock validation and failed while the
MOSCIM
bit in the
MOSCCTL register is clear, generating a reset event.
1
-
RW
MOSCFAIL
16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
15:13
December 13, 2013
278
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