Texas Instruments CC2650DK Manuale Utente
Cortex-M3 Processor Registers
Table 2-111. NVIC_IABR0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
ACTIVE2
R
X
Reading 0 from this bit implies that interrupt line 2 is not active.
Reading 1 from this bit implies that the interrupt line 2 is active (See
EVENT:CPUIRQSEL2.EV for details).
Reading 1 from this bit implies that the interrupt line 2 is active (See
EVENT:CPUIRQSEL2.EV for details).
1
ACTIVE1
R
X
Reading 0 from this bit implies that interrupt line 1 is not active.
Reading 1 from this bit implies that the interrupt line 1 is active (See
EVENT:CPUIRQSEL1.EV for details).
Reading 1 from this bit implies that the interrupt line 1 is active (See
EVENT:CPUIRQSEL1.EV for details).
0
ACTIVE0
R
X
Reading 0 from this bit implies that interrupt line 0 is not active.
Reading 1 from this bit implies that the interrupt line 0 is active (See
EVENT:CPUIRQSEL0.EV for details).
Reading 1 from this bit implies that the interrupt line 0 is active (See
EVENT:CPUIRQSEL0.EV for details).
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SWCU117A – February 2015 – Revised March 2015
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