Texas Instruments 2.25A Inverting Buck Boost Regulator Evaluation Module TPS5430EVM-342 TPS5430EVM-342 Scheda Tecnica
Codici prodotto
TPS5430EVM-342
3
Board Layout
3.1
Layout
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Board Layout
Figure 6. Power Up, V
OUT
Relative to V
IN
This section describes the TPS5430EVM-342 board layout and layer illustrations.
through
display the board layout for the TPS5430EVM-342. The topside layer of the
TPS5430EVM-342 is laid out in a manner typical of a user application. The top and bottom layers are
2-oz. copper.
2-oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS5430 and a large area filled with ground. The bottom layer
contains ground and some signal routing. The top and bottom and internal ground traces are connected
with multiple vias placed around the board including four vias directly under the TPS5430 device to
provide a thermal path from the PowerPAD™ land to ground.
contains ground and some signal routing. The top and bottom and internal ground traces are connected
with multiple vias placed around the board including four vias directly under the TPS5430 device to
provide a thermal path from the PowerPAD™ land to ground.
The input decoupling capacitor (C1) and bootstrap capacitor (C3) are all located as close to the IC as
possible. In addition, the voltage set point resistor divider components are also kept close to the IC. The
voltage divider network ties to the output voltage at the point of regulation, adjacent to the output capacitor
C3.
possible. In addition, the voltage set point resistor divider components are also kept close to the IC. The
voltage divider network ties to the output voltage at the point of regulation, adjacent to the output capacitor
C3.
SLVU243 – May 2008
TPS5430EVM-342 2.25-A, Inverting Buck-Boost Regulator Evaluation Module
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