Texas Instruments TPS54336 Synchronous Step-Down Converter Evaluation Module TPS54336EVM-556 TPS54336EVM-556 Scheda Tecnica
Codici prodotto
TPS54336EVM-556
V
= 2 V / div
OUT
Time = 2 msec / div
EN = 5 V / div
V = 20 V / div
IN
SS = 2 V / div
V
= 2 V / div
OUT
Time = 2 msec / div
EN = 5 V / div
V = 20 V / div
IN
SS = 2 V / div
Test Setup and Results
2.10 Powering Down
and
show the start-up waveforms for the TPS54336EVM-556. In
, the output
voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R1
and R2 resistor divider network. In
and R2 resistor divider network. In
, the output is inhibited by using a jumper at JP1 to tie EN to
GND. The input voltage for these plots is 24 V and the load is 5
Ω
.
Figure 13. TPS54336EVM-556 Shut-down Relative to V
IN
Figure 14. TPS54336EVM-556 Shut-down Relative to EN
11
SLVU927 – June 2013
TPS54336EVM-556 3-A Regulator Evaluation Module
Copyright © 2013, Texas Instruments Incorporated