Texas Instruments TAS5176DDW6 Evaluation Module TAS5176DDW6EVM TAS5176DDW6EVM Scheda Tecnica
Codici prodotto
TAS5176DDW6EVM
www.ti.com
1.2
PCB Key Map
SPEAKER OUTPUTS
6 CHANNEL
POWER STAGE
TAS5176
INPUT SIGNAL
INTERFACE (J60)
CONTROL
INTERFACE(J40)
J104
P
S
U
IN
T
E
R
F
A
C
E
(J
90
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V
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J103
J105
J106
J102
J101
TAS5086
3.3V
Regulator
2
Quick Setup Guide
2.1
Electrostatic Discharge Warning
Quick Setup Guide
The physical structure of the TAS5176DDW6EVM is shown in
.
Figure 2. Physical Structure of the TAS5176DDW6EVM (Approximate Layout)
This chapter describes the TAS5176DDW6EVM board in regards to power supplies and system
interfaces. The chapter provides information regarding handling and unpacking, absolute operating
conditions, and a description of the factory default switch and jumper configuration.
interfaces. The chapter provides information regarding handling and unpacking, absolute operating
conditions, and a description of the factory default switch and jumper configuration.
This chapter provides a step-by-step guide to configuring the TAS5176DDW6EVM for device evaluation.
Many of the components on the TAS5176DDW6EVM are susceptible to damage by electrostatic
discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking
and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking
and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
CAUTION
Failure to observe ESD handling procedures may result in damage to EVM
components.
components.
SLOU209A – September 2007 – Revised October 2007
TAS5176DDW6EVM
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