Texas Instruments SMV512K32-SP Evaluation Board SMV512K32-CVAL SMV512K32-CVAL Scheda Tecnica

'

–

This document outlines the basic steps and functions that are required to ensure proper operation of the
SMV512K32-CVAL breakout evaluation board. It works in tandem with a customers

’

pattern generation

and capture hardware to demonstrate the memory function features of the 16-Mbit asynchronous SRAM
memory.

1

Overview

.....................................................................................................................

2

Hardware Description

......................................................................................................

3

Device Insertion

.............................................................................................................

4

Schematics

...................................................................................................................

4.1

Element Schematics

...............................................................................................

4.2

Printed-Circuit-Board Layout Schematics

.......................................................................

5

EVM Connectors

...........................................................................................................

5.1

Description

........................................................................................................

1

SMV512K32-SP Block Diagram

..........................................................................................

2

SMV512K32-SP 76-Pin QFP (HFG) Package

..........................................................................

3

SMV512K32-CVAL ENPLAS Socket

.....................................................................................

4

SMV512K32-CVAL Elemental Schematic

...............................................................................

5

PCB Layout Layer 1

........................................................................................................

6

PCB Layout Layer 2

........................................................................................................

7

PCB Layout Layer 3

........................................................................................................

8

PCB Layout Layer 4

........................................................................................................

9

PCB Layout Layer 5

.......................................................................................................

10

PCB Layout Layer 6

.......................................................................................................

11

SMV512K32-CVAL

........................................................................................................

1

SLVU571

–

January 2012

Copyright

©

2012, Texas Instruments Incorporated