Texas Instruments CDCM9102 Evaluation Module CDCM9102EVM CDCM9102EVM Scheda Tecnica
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CDCM9102EVM
User's Guide
SCAU048 – March 2012
CDCM9102EVM Clock Evaluation Module
CDCM9102EVM is the evaluation module (EVM) for the CDCM9102, a low-jitter clock generator that
provides reference clocks for communications standards such as PCI Express. This clock generator is
easy to configure and use. It provides two, 100-MHz, differential clock ports. The supported output types
for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. An ac-coupled network supports
HCSL signaling. The user configures the desired output buffer type by strapping device pins. Additionally,
the EVM has a single-ended, 25-MHz clock output port. Uses for this port include general-purpose
clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All
generated clocks derive from a single, 25-MHz crystal that is external to the device. This fully assembled
and factory-tested evaluation board allows complete validation of all device functions.
provides reference clocks for communications standards such as PCI Express. This clock generator is
easy to configure and use. It provides two, 100-MHz, differential clock ports. The supported output types
for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. An ac-coupled network supports
HCSL signaling. The user configures the desired output buffer type by strapping device pins. Additionally,
the EVM has a single-ended, 25-MHz clock output port. Uses for this port include general-purpose
clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All
generated clocks derive from a single, 25-MHz crystal that is external to the device. This fully assembled
and factory-tested evaluation board allows complete validation of all device functions.
Contents
1
Features
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2
General Description
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3
Signal Path and Control Circuitry
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4
Getting Started
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4.1
Power-Supply Connection
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5
Input Clock Selection
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5.1
Configuring a Crystal Input
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5.2
Configuring a Single-Ended Input
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6
Operating Mode Selection
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6.1
Output Buffer Type Selection
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6.2
Using ENABLE and RESET Pins
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7
Output Buffer Termination
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7.1
Output Buffer Examples
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7.2
Availability of Optional Output
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8
Schematic
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List of Figures
1
CDCM9102EVM Evaluation Module
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2
CDCM9102EVM Configuration With Parallel-Load Resonant Crystal Clock Source
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3
Single-Ended Connection Configuration
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4
EVM Output Termination Options
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5
CDCM9102EVM Schematic
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List of Tables
1
Output Buffer Options
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2
Power-Down Configuration
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3
Reset Configuration
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1
SCAU048 – March 2012
CDCM9102EVM Clock Evaluation Module
Copyright © 2012, Texas Instruments Incorporated