Texas Instruments DS90UR916Q Evaluation Module SERDESUR-916ROS/NOPB SERDESUR-916ROS/NOPB Scheda Tecnica
Codici prodotto
SERDESUR-916ROS/NOPB
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
DS90UR916Q 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement
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FEATURES
DESCRIPTION
The DS90UR916Q FPD-Link II deserializer operates
2
•
5 – 65 MHz PCLK support (140 Mbps – 1.82
with the DS90UR905Q FPD-Link II serializer to
Gbps)
deliver 24-bit digital video data over a single
•
RGB888 + VS, HS, DE Support
differential pair. The DS90UR916Q provides features
•
Image Enhancement - White Balance LUTs and
designed to enhance image quality at the display.
The high speed serial bus scheme of FPD-Link II
The high speed serial bus scheme of FPD-Link II
Adaptive Hi-FRC Dithering
greatly eases system design by eliminating skew
•
AC Coupled STP Interconnect Cable up to 10
problems between clock and data, reduces the
Meters
number of connector pins, reduces the interconnect
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@ Speed Link BIST Mode and Reporting Pin
size, weight, and cost, and overall eases PCB layout.
In addition, internal DC balanced decoding is used to
In addition, internal DC balanced decoding is used to
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I2C Compatible Serial Control Bus
support AC-coupled interconnects.
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Power Down Mode Minimizes Power
Dissipation
Dissipation
The DS90UR916Q Des (deserializer) recovers the
data (RGB) and control signals and extracts the clock
data (RGB) and control signals and extracts the clock
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1.8V or 3.3V Compatible LVCMOS I/O Interface
from the serial stream. The Des locks to the incoming
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Automotive Grade Product: AEC-Q100 Grade 2
serial data stream without the use of a training
Qualified
sequence or special SYNC patterns, and does not
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>8 kV HBM and ISO 10605 ESD Rating
require a reference clock. A link status (LOCK) output
signal is provided. The DS90UR916Q is ideally suited
signal is provided. The DS90UR916Q is ideally suited
•
FAST Random Ddata Lock; No Reference
for 24-bit color applications. White balance lookup
Clock Required
tables and adaptive Hi-FRC dithering provide the user
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Adjustable Input Receiver Equalization
a cost-effective means to enhance display image
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LOCK (Real Time Link Status) Reporting Pin
quality.
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EMI Minimization on Output Parallel Bus
Serial transmission is optimized with user selectable
(SSCG)
receiver equalization. EMI is minimized by the use of
low voltage differential signaling, output slew control,
low voltage differential signaling, output slew control,
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Output Slew Control (OS)
and the Des may be configured to generate Spread
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Backward Compatible Mode for Operation with
Spectrum Clock and Data on its parallel outputs.
Older Generation Devices
The DS90UR916Qis offered in a 60-pin WQFN
package. It is specified over the automotive AEC-
package. It is specified over the automotive AEC-
APPLICATIONS
Q100 grade 2 temperature range of -40°C to +105°C.
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Automotive Display for Navigation
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Automotive Display for Entertainment
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date.
Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.