Texas Instruments Evaluation Module for Dual, 200 mA Output, Low Noise, High PSRR, Low-Dropout Regulator TLV7101828EVM-5 TLV7101828EVM-595 Scheda Tecnica

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TLV7101828EVM-595
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User's Guide
SLVU404 – September 2010
TLV7101828EVM-595
This user’s guide describes the characteristics, operation, and use of the TLV7101828EVM-595
Evaluation Module (EVM) as a reference design for engineering demonstration and evaluation of the
TLV710xxxx dual-channel, low-dropout (LDO) linear regulator. Included in this user’s guide are setup
instructions, a schematic diagram, layout and thermal guidelines, a bill of materials, and test results.
Contents
1
Introduction
..................................................................................................................
2
Setup
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2.1
Input/Output Connectors and Jumper Descriptions
...........................................................
2.2
Soldering Guidelines
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2.3
Equipment Interconnect
...........................................................................................
3
Operation
.....................................................................................................................
4
Test Results
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4.1
Turnon Sequence
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4.2
OUT 1 Load Transient
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4.3
OUT 2 Load Transient
.............................................................................................
5
Thermal Guidelines
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6
Board Layout
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7
Schematic and Bill of Materials
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7.1
Schematic
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7.2
Bill of Materials
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List of Figures
1
Turnon Sequence: Ch 3 VIN – Turnon to 4 V, Ch2 OUT 2 – 2.8-V Turnon Ramp, Ch1 OUT 1 – 1.8-V
Turnon Ramp
................................................................................................................
2
Ch 1 OUT 1 -1.8-V Load Transient Response for VIN at 3.3 V, Ch2 OUT 2 – 2.8-V Crosstalk Response,
Ch 4 OUT 1 Load Current Transient
.....................................................................................
3
Ch 1 OUT 1 -1.8-V Crosstalk Response, Ch2 OUT 2 – 2.8-V Transient Response for VIN at 3.3-V, Ch 3
OUT 2 Load Current Transient
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4
Assembly Layer
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5
Layer One Routing
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6
Layer Two Routing
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7
Bottom Layer Routing
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8
TLV7101828EVM-595 Schematic
........................................................................................
List of Tables
1
Thermal Resistance,
q
_ja , and Maximum Power Dissipation
........................................................
2
TLV7101828EVM-595 Bill of Materials
...................................................................................
1
SLVU404 – September 2010
TLV7101828EVM-595
Copyright © 2010, Texas Instruments Incorporated