Texas Instruments DS100KR800EVK evaluation board DS100KR800EVK/NOPB DS100KR800EVK/NOPB Scheda Tecnica
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DS100KR800EVK/NOPB
SNLS340D – NOVEMBER 2011 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTIONS
The DS100KR800 is a low power media compensation 8 channel repeater optimized for 10G–KR. The
DS100KR800 compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The
DS100KR800 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and
SMBus Master Mode (ENSMB = float) to load register informations from external EEPROM; please refer to
SMBUS Master Mode for additional information.
DS100KR800 compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The
DS100KR800 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and
SMBus Master Mode (ENSMB = float) to load register informations from external EEPROM; please refer to
SMBUS Master Mode for additional information.
Pin Control Mode:
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically
adjusted per the
can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically
adjusted per the
below. The receiver electrical idle detect threshold is also adjustable via the
SD_TH pin.
SMBUS Mode:
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain
active unless their respective registers are written to and the appropriate override bit is set, in which case they
are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is driven low all registers are
reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain
active unless their respective registers are written to and the appropriate override bit is set, in which case they
are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is driven low all registers are
reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting when the
device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are set by
registers.
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting when the
device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are set by
registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control
settings when ENSMB=0.
settings when ENSMB=0.
Table 1. 4–Level Control Pin Settings
Pin Setting
Description
(1)
Voltage at Pin
0
Tie 1k
Ω
to GND
0.03 x VDD
R
Tie 20k
Ω
to GND
1/3 x VDD
Float
Float (leave pin open)
2/3 x VDD
1
Tie 1k
Ω
to VDD
0.98 x VDD
(1)
The above required resistor value is for a single device. When there are multiple devices connected to the pull-up / pull-down resistor,
the value must scale with the number of devices. If 4 devices are connected to a single pull-up or pull-down, the 1k
the value must scale with the number of devices. If 4 devices are connected to a single pull-up or pull-down, the 1k
Ω
resistor value
should be 250
Ω
. For the 20k
Ω
to GND, this should also scale to 5k
Ω
.
3.3V or 2.5V Supply Mode Operation
The DS100KR800 has an optional internal voltage regulator to provide the 2.5V supply to the device. In 3.3V
mode, the VIN pin = 3.3V is used to supply power to the device and the VDD pins should be left open. The
internal regulator will provide the 2.5V to the VDD pins of the device and a 0.1 uF cap is needed at each of 5
VDD pins for power supply de-coupling (total capacitance should be
mode, the VIN pin = 3.3V is used to supply power to the device and the VDD pins should be left open. The
internal regulator will provide the 2.5V to the VDD pins of the device and a 0.1 uF cap is needed at each of 5
VDD pins for power supply de-coupling (total capacitance should be
≤
0.5 uF). The VDD_SEL pin must be tied to
GND to enable the internal regulator. In 2.5V mode, the VIN pin should be left open and 2.5V supply must be
applied to the VDD pins. The VDD_SEL pin must be left open (no connect) to disable the internal regulator.
applied to the VDD pins. The VDD_SEL pin must be left open (no connect) to disable the internal regulator.
10
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