Texas Instruments Evaluation Board for the LMP7312 LMP7312MAEVAL/NOPB LMP7312MAEVAL/NOPB Scheda Tecnica
Codici prodotto
LMP7312MAEVAL/NOPB
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LMP7312 Evaluation Board User Guide
(551600360-001 REV A)
This evaluation board contains the LMP7312, along with a SPI command generator to program the registers
in the LMP7312
.
Connectors, Jumpers, Test Point
POWER SUPPLY
+Vs
banana plug for the positive power
supply of the LMP7312 and the on-
board SPI command generator.
supply of the LMP7312 and the on-
board SPI command generator.
VIO
banana plug to power the SPI of the
LMP7312 when an external micro is
used to program the SPI.
LMP7312 when an external micro is
used to program the SPI.
GND
banana plug for ground connection.
SIGNAL CONNECTORS
Input signals
+IN_CL banana plug for non-inverting input of
+IN_CL banana plug for non-inverting input of
the amplification pair.
-IN_CL banana plug for inverting input of the
amplification pair.
+IN_LS BNC for non-inverting input of the
attenuation pair.
-IN_LS
BNC for inverting input of the
attenuation pair.
attenuation pair.
J7
14-pin
header
available
for
microcontroller connection. The pin out
is shown in Table 3.
is shown in Table 3.
Reference Signals
V
ocm
banana plug for the common mode
output
output
signals
and
the
output
configuration
(single
ended,
differential).
See
the
Output
Configuration section.
VR
banana plug for the output reference
when the output of the LMP7312 is
used in single ended mode.
when the output of the LMP7312 is
used in single ended mode.
Output signals
OUT-
BNC for the inverting Output in the
differential output configuration
differential output configuration
OUT+
BNC for the non-inverting output.
DP
Differential Probe Header connector.
P1
5-pin header for ADC141S626 or
ADC161S626 Eval Board connection.
ADC161S626 Eval Board connection.
JUMPERS
The eval board has 6 jumpers:
J1 connects the CSB pin of the LMP7312 to
J1 connects the CSB pin of the LMP7312 to
either the onboard SPI commands generator
or to pin 1 of J7.
or to pin 1 of J7.
J2 connects the SCK pin of the LMP7312 to
either the onboard SPI commands generator
or to pin 3 of J7.
or to pin 3 of J7.
J3 connects the SDI pin of the LMP7312 to
either the onboard SPI commands generator
or to pin 5 of J7.
or to pin 5 of J7.
J4 connects the -VOUT/VR pin of the LMP7312
either to the VR reference or to the LOAD.
(see the Output Configuration section).
(see the Output Configuration section).
J5 connects the VOCM pin of the LMP7312 to
either the ground or to the VOCM reference.
(see the Output Configuration section).
(see the Output Configuration section).
J6 connects the VIO pin of the LMP7312 to
either the +Vs plug or to the VIO plug.
TEST POINTS
The test points are connected as follows:
TP1
TP1
GND
TP2
-IN pin
TP3
-VIN pin
TP4
-VOUT/VR pin
TP5
+IN pin
TP6
+VIN pin
TP7
+VOUT pin
TP8
VR
TP9
VOCM
TP10 +Vs
TP11
VIO