Microchip Technology DV164136 Scheda Tecnica
© 2008 Microchip Technology Inc.
DS80417A-page 1
PIC18F87J11 FAMILY
The PIC18F87J11 Family parts you have received con-
form functionally to the Device Data Sheet
(DS39778C), except for the anomalies described
below.
form functionally to the Device Data Sheet
(DS39778C), except for the anomalies described
below.
Any Data Sheet Clarification issues related to the
PIC18F87J11 Family devices will be reported in a sep-
arate Data Sheet errata. Please check the Microchip
web site for any existing issues.
PIC18F87J11 Family devices will be reported in a sep-
arate Data Sheet errata. Please check the Microchip
web site for any existing issues.
The following silicon errata apply only to
PIC18F87J11 Family devices with these Device/
Revision IDs:
PIC18F87J11 Family devices with these Device/
Revision IDs:
1.
Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C™ slave reception, the
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next byte
being received.
being received.
Date Codes that pertain to this issue:
All engineering and production devices.
Part Number
Device ID
Revision ID
PIC18F66J11
0100 0100 010
0 0100
PIC18F66J16
0100 0100 011
0 0100
PIC18F67J11
0100 0100 100
0 0100
PIC18F86J11
0100 0100 111
0 0100
PIC18F86J16
0100 0101 000
0 0100
PIC18F87J11
0100 0101 001
0 0100
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
PIC18F87J11 Family Rev. A4 Silicon Errata