Microchip Technology MA330028 Scheda Tecnica
2011-2014 Microchip Technology Inc.
DS80000533H-page 7
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
Silicon Errata Issues
1.
Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
the div.sd instruction.
Affected Families and Silicon Revisions
2.
Module: CPU
Table Write (TBLWTL, TBLWTH) instructions cannot
be the first or last instruction of a DO loop.
be the first or last instruction of a DO loop.
Work around
None.
Affected Families and Silicon Revisions
3.
Module: SPI
When using the Frame Sync pulse output feature
(FRMEN bit (SPIxCON2<15>) = 1) in Master
mode (SPIFSD bit (SPIxCON2<14>) = 0), the
Frame Sync pulse is not being generated
with an active-low pulse (FRMPOL bit
(SPIxCON2<13>) = 0).
(FRMEN bit (SPIxCON2<15>) = 1) in Master
mode (SPIFSD bit (SPIxCON2<14>) = 0), the
Frame Sync pulse is not being generated
with an active-low pulse (FRMPOL bit
(SPIxCON2<13>) = 0).
Work around
The SSx pin is used as the Frame Sync pulse
when the Frame Sync pulse output feature is used.
Mapping the SSx input function and output
function to the same pad, by using the Peripheral
Pin Select (PPS) feature, resolves this issue.
when the Frame Sync pulse output feature is used.
Mapping the SSx input function and output
function to the same pad, by using the Peripheral
Pin Select (PPS) feature, resolves this issue.
Affected Families and Silicon Revisions
4.
Module: SPI
When in SPI Slave mode (MSTEN bit
(SPIxCON1<5>) = 0) and using the Frame Sync
pulse output feature (FRMEN bit
(SPIxCON2<15>) = 1) in Slave mode (SPIFSD bit
(SPIxCON2<14>) = 0), the Frame Sync Pulse
Edge Select bit must be set to ‘0’ (FRMDLY bit
(SPIxCON2<1>) = 0).
(SPIxCON1<5>) = 0) and using the Frame Sync
pulse output feature (FRMEN bit
(SPIxCON2<15>) = 1) in Slave mode (SPIFSD bit
(SPIxCON2<14>) = 0), the Frame Sync Pulse
Edge Select bit must be set to ‘0’ (FRMDLY bit
(SPIxCON2<1>) = 0).
Work around
There is no work around. The Frame Sync Pulse
Edge Select bit, FRMDLY, cannot be set to
produce a Frame Sync pulse that coincides with
the first bit clock.
Edge Select bit, FRMDLY, cannot be set to
produce a Frame Sync pulse that coincides with
the first bit clock.
Affected Families and Silicon Revisions
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current.
errata issues from all revisions of silicon,
previous as well as current.
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7