Microchip Technology MCP3421DM-WS Scheda Tecnica

© 2009 Microchip Technology Inc.

DS22003E-page 9

The descriptions of the pins are listed in 

 

V

IN

+ and V

IN

- are differential signal input pins. The

MCP3421 device accepts a fully differential analog
input signal which is connected on the V

IN

+ and V

IN

-

input pins. The differential voltage that is converted is
defined by V

IN

 = (V

IN

+ - V

IN

-) where V

IN

+ is the voltage

applied at the V

IN

+ pin and V

IN

- is the voltage applied

at the V

IN

- pin. The user can also connect V

IN

-

 pin to

V

SS

 for a single-ended operation. See 

 for

differential and single-ended connection examples. 

The input signal level is amplified by the programmable
gain amplifier (PGA) before the conversion. The
differential input voltage should not exceed an absolute
of (V

REF

/PGA) for accurate measurement, where V

REF

is the internal reference voltage (2.048V) and PGA is
the PGA gain setting. The converter output code will
saturate if the input range exceeds (V

REF

/PGA).

The absolute voltage range on each of the differential
input pins is from V

SS

-0.3V to V

DD

+0.3V. Any voltage

above or below this range will cause leakage currents
through the Electrostatic Discharge (ESD) diodes at
the input pins. This ESD current can cause unexpected
performance of the device. The common mode of the
analog inputs should be chosen such that both the
differential analog input range and the absolute voltage
range on each pin are within the specified operating
range defined in 

Characteristics” and Section 4.0 “Description of
Device Operation”.

See 

Section 4.5 “Input Voltage Range” for more

details of the input voltage range. 

 shows the input structure of the device. The

device uses a switched capacitor input stage at the
front end. C

PIN

 is the package pin capacitance and

typically about 4 pF. D

1

 and D

2

 are the ESD diodes.

C

SAMPLE

 is the differential input sampling capacitor.

 

V

DD

 is the power supply pin for the device. This pin

requires an appropriate bypass capacitor of about
0.1 µF (ceramic) to ground. An additional 10 µF
capacitor (tantalum) in parallel is also recommended
to further attenuate high frequency noise present in
some application boards. The supply voltage (V

DD

)

must be maintained in the 2.7V to 5.5V range for
specified operation. 

V

SS

 is the ground pin and the current return path of the

device. The user must connect the V

SS

 pin to a ground

plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the V

SS

 pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit
board. 

 

SCL is the serial clock pin of the I

2

C interface. The

MCP3421 acts only as a slave and the SCL pin
accepts only external serial clocks. The input data
from the Master device is shifted into the SDA pin on
the rising edges of the SCL clock and output from the
MCP3421 occurs at the falling edges of the SCL clock.
The SCL pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the V

DD

 line

to the SCL pin. Refer to 

Communications” for more details of I

2

C Serial

Interface communication.

1

V

IN

+

Positive Differential Analog Input Pin

2

V

SS

Ground Pin

3

SCL

Serial Clock Input Pin of the I

2

C Interface

4

SDA

Bidirectional Serial Data Pin of the I

2

C Interface

5

V

DD

Positive Supply Voltage Pin

6

V

IN

-

Negative Differential Analog Input Pin