Microchip Technology DV164136 Scheda Tecnica
2007-2012 Microchip Technology Inc.
DS39778E-page 81
PIC18F87J11 FAMILY
REGISTER 6-3:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
R-x
U-0
R/W-0
U-0
U-0
U-0
U-0
REGSLP
LVDSTAT
—
ADSHR
—
—
—
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
REGSLP:
Voltage Regulator Low-Power Operation Enable bit
For details of bit operation, see
bit 6
LVDSTAT:
LVD Status bit
1
= V
DDCORE
> 2.45V
0
= V
DDCORE
< 2.45V
bit 5
Unimplemented
: Read as ‘0’
bit 4
ADSHR:
Shared Address SFR Select bit
1
= Alternate SFR is selected
0
= Default (Legacy) SFR is selected
bit 3-1
Unimplemented
: Read as ‘0’
bit 0
SWDTEN:
Software Controlled Watchdog Timer Enable bit
For details of bit operation, see