Microchip Technology MA240017 Scheda Tecnica
PIC24F16KA102 FAMILY
DS39927C-page 24
2008-2011 Microchip Technology Inc.
FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
TABLE 3-1:
CPU CORE REGISTERS
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Data Bus
Instruction Reg
16
16 x 16
W Register Array
Divide
Support
ROM Latch
16
EA MUX
RAGU
WAGU
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Data RAM
Address
Latch
Control Signals
to Various Blocks
Program Memory
Data Latch
Address Bus
16
Li
te
ra
l Da
ta
16
16
Hardware
Multiplier
16
To Peripheral Modules
Address Latch
Data EEPROM
Register(s) Name
Description
W0 through W15
Working Register Array
PC
23-Bit Program Counter
SR
ALU STATUS Register
SPLIM
Stack Pointer Limit Value Register
TBLPAG
Table Memory Page Address Register
PSVPAG
Program Space Visibility Page Address Register
RCOUNT
Repeat Loop Counter Register
CORCON
CPU Control Register