Microchip Technology MA240017 Scheda Tecnica
2008-2011 Microchip Technology Inc.
DS39927C-page 63
PIC24F16KA102 FAMILY
8.0
INTERRUPT CONTROLLER
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the CPU. It has the following features:
• Up to eight processor exceptions and
peripheral interrupt request signals to a single interrupt
request signal to the CPU. It has the following features:
• Up to eight processor exceptions and
software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• Unique vector for each interrupt or exception
• Interrupt Vector Table (IVT) with up to 118 vectors
• Unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
8.1
Interrupt Vector (IVT) Table
The IVT is displayed in
. The IVT resides in
the program memory, starting at location, 000004h.
The IVT contains 126 vectors, consisting of eight
non-maskable trap vectors, plus, up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt
associated with Vector 0 will take priority over interrupts
at any other vector address.
PIC24F16KA102 family devices implement
non-maskable traps and unique interrupts; these are
summarized in
The IVT contains 126 vectors, consisting of eight
non-maskable trap vectors, plus, up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt
associated with Vector 0 will take priority over interrupts
at any other vector address.
PIC24F16KA102 family devices implement
non-maskable traps and unique interrupts; these are
summarized in
8.1.1
ALTERNATE INTERRUPT VECTOR
TABLE (AIVT)
TABLE (AIVT)
. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the
interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run-time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the
interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run-time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
8.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the Program Counter (PC) to
zero. The microcontroller then begins program execu-
tion at location, 000000h. The user programs a GOTO
instruction at the Reset address, which redirects the
program execution to the appropriate start-up routine.
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the Program Counter (PC) to
zero. The microcontroller then begins program execu-
tion at location, 000000h. The user programs a GOTO
instruction at the Reset address, which redirects the
program execution to the appropriate start-up routine.
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the Interrupt Controller, refer to the
“PIC24F Family Reference Manual”
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the Interrupt Controller, refer to the
“PIC24F Family Reference Manual”
,
Section 8. “Interrupts”
(DS39707).
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET
instruction.