Microchip Technology AC164337 Scheda Tecnica
dsPIC30F1010/202X
DS70000178D-page 210
2006-2014 Microchip Technology Inc.
FIGURE 18-6:
FRC TUNE DITHER LOGIC BLOCK DIAGRAM
FIGURE 18-7:
RESET SYSTEM BLOCK DIAGRAM
D Q
CLK
3
TUNE BIts to FRC
All Zero Detect
TSEQEN in OSCCON
15
ROLL<3>
0
1
TSEQ7
4
D
Q0
CLK Q
D
Q1
CLK Q
D
Q2
CLK Q
D
Q3
CLK Q
D
Q4
CLK Q
D
Q5
CLK Q
D
Q6
CLK Q
D
Q7
CLK Q
D
Q8
CLK Q
D
Q9
CLK Q
D Q10
CLK Q
D Q11
CLK Q
D Q12
CLK Q
D Q13
CLK Q
D Q14
CLK Q
LFSR
PWM PS
TSEQ6 TSEQ5 TSEQ4
0
15
OSCTUN2
TSEQ3 TSEQ2 TSEQ1 TUN
0
15
OSCTUN
3
4
3
12
12 11
7
11
0
1
2
2
3
4
5
6
8
4
5
6
8
4
MU
X
ROLL Counter
ROLL<5:3> ROLL<2:0>
MU
X
4
Shift Enable for LFSR
4
PRCDEN in OSCCON
S
R
Q
MCLR
V
DD
V
DD
Rise
Detect
POR
SYSRST
Sleep or Idle
WDT
Module
Digital
Glitch Filter
Trap Conflict
Illegal Opcode/
Uninitialized W Register
Uninitialized W Register
RESET
Instruction