Microchip Technology MCP1630DM-DDBS1 Scheda Tecnica

DS41211D-page 8

©

 2007 Microchip Technology Inc.

2.2.1

GENERAL PURPOSE REGISTER 
FILE

The register file is organized as 128 x 8 in the
PIC12F683. Each register is accessed, either directly
or indirectly, through the File Select Register FSR (see
Section 2.4 “Indirect Addressing, INDF and FSR
Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.

The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature. 

Indirect addr.

TMR0

PCL

STATUS

FSR

GPIO

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

7Fh

BANK 0

Unimplemented data memory locations, read as ‘

0

’.

Note 1: Not a physical register.

CMCON0

VRCON

General

Purpose

Registers

96 Bytes

EEDAT

EEADR

EECON2

File

Address

File

Address

WPU

IOC

Indirect addr.

OPTION_REG

PCL

STATUS

FSR

TRISIO

PCLATH

INTCON

PIE1

PCON

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh
A0h

FFh

BANK 1

ADRESH

ADCON0

EECON1

ADRESL

ANSEL

BFh

General

Purpose

Registers

32 Bytes

Accesses 70h-7Fh

F0h

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

WDTCON

CMCON1

OSCCON

OSCTUNE

PR2

C0h

EFh