Microchip Technology MCP1630DM-DDBS1 Scheda Tecnica

©

 2007 Microchip Technology Inc.

DS41211D-page 99

If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP

™

 for verification purposes.

Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

PC

Instruction

Fetched

Instruction

Executed

PC

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2

0004h

0005h

Dummy Cycle

T

OST

PC + 2

XT, HS or LP Oscillator mode assumed.

T

OST

 = 1024 T

OSC

 (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes.

GIE = 

1

 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 

0

, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

The entire data EEPROM and Flash pro-
gram memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory
Programming Specification” (DS41204)
for more information.