Microchip Technology MCP1630DM-DDBS1 Scheda Tecnica
©
2007 Microchip Technology Inc.
DS41211D-page 51
PIC12F683
8.0
COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The analog
comparator module includes the following features:
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The analog
comparator module includes the following features:
• Multiple comparator configurations
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
• Timer1 gate (count enable)
• Output synchronization to Timer1 clock input
• Programmable voltage reference
8.1
Comparator Overview
The comparator is shown in Figure 8-1 along with the
relationship between the analog input levels and the
digital output. When the analog voltage at V
relationship between the analog input levels and the
digital output. When the analog voltage at V
IN
+ is less
than the analog voltage at V
IN
-, the output of the
comparator is a digital low level. When the analog
voltage at V
voltage at V
IN
+ is greater than the analog voltage at
V
IN
-, the output of the comparator is a digital high level.
FIGURE 8-1:
SINGLE COMPARATOR
FIGURE 8-2:
COMPARATOR OUTPUT BLOCK DIAGRAM
–
+
V
IN
+
V
IN
-
Output
Output
V
IN
+
V
IN
-
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
comparator represents the uncertainty
due to input offsets and response time.
CMSYNC
D
Q
EN
To COUT pin
RD CMCON0
Set CMIF bit
MUL
T
IP
LE
X
X
Por
t Pi
ns
ns
Q3*RD CMCON0
Reset
To Data Bus
CINV
Timer1
clock source
(1)
0
1
To Timer1 Gate
Note 1:
Comparator output is latched on falling edge of Timer1 clock source.
2:
Q1 and Q3 are phases of the four-phase system clock (F
OSC
).
3:
Q1 is held high during Sleep mode.
D
Q
D
Q
EN
CL
Q1