Microchip Technology TDGL019 Scheda Tecnica
PIC32MX1XX/2XX
DS60001168F-page 160
© 2011-2014 Microchip Technology Inc.
REGISTER 14-1:
IC
X
CON: INPUT CAPTURE ‘x’ CONTROL REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
ON
(1)
—
SIDL
—
—
—
FEDGE
C32
7:0
R/W-0
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
P = Programmable bit
r = Reserved bit
bit 31-16
Unimplemented:
Read as ‘0’
bit 15
ON:
Input Capture Module Enable bit
(1)
1
= Module is enabled
0
= Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14
Unimplemented:
Read as ‘0’
bit 13
SIDL:
Stop in Idle Control bit
1
= Halt in Idle mode
0
= Continue to operate in Idle mode
bit 12-10
Unimplemented:
Read as ‘0’
bit 9
FEDGE:
First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)
1
= Capture rising edge first
0
= Capture falling edge first
bit 8
C32:
32-bit Capture Select bit
1
= 32-bit timer resource capture
0
= 16-bit timer resource capture
bit 7
ICTMR:
Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)
0
= Timer3 is the counter source for capture
1
= Timer2 is the counter source for capture
bit 6-5
ICI<1:0>:
Interrupt Control bits
11
= Interrupt on every fourth capture event
10
= Interrupt on every third capture event
01
= Interrupt on every second capture event
00
= Interrupt on every capture event
bit 4
ICOV:
Input Capture Overflow Status Flag bit (read-only)
1
= Input capture overflow has occurred
0
= No input capture overflow has occurred
bit 3
ICBNE:
Input Capture Buffer Not Empty Status bit (read-only)
1
= Input capture buffer is not empty; at least one more capture value can be read
0
= Input capture buffer is empty
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.