Microchip Technology MCP3421DM-WS Scheda Tecnica
© 2009 Microchip Technology Inc.
DS39632E-page 261
PIC18F2455/2550/4455/4550
FIGURE 20-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 20-7:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
RC7/RX/DT/SDO pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0
bit 1
bit 2
bit 6
bit 7
TXEN bit
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
SPPIF
(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
SPPIE
(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
SPPIP
(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
TXREG
EUSART Transmit Register
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
BAUDCON
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGH
EUSART Baud Rate Generator Register High Byte
SPBRG
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.