Microchip Technology MA180021 Manuale Utente
Important Notes and Migration Tips
© 2007 Microchip Technology Inc.
DS51678A-page 9
2.4.2
Oscillator Configuration
The PIC18F87J50 family devices use the same 96 MHz PLL found in prior full-speed
USB microcontrollers, such as the PIC18F4550, but the implementation of the surround-
ing clock structure is slightly different. When migrating up to the PIC18F87J50 family of
devices, the most important change is the PLL does not automatically start when the
microcontroller is powered on, even if it is programmed to use one of the PLL-enabled
modes (e.g., HS+PLL). This allows the microcontroller to start up at less than the
maximum operating frequency. This can potentially be advantageous when running from
a decaying power source (such as a battery), where the applied voltage may not be
adequate for maximum frequency operation. For applications such as these, the
WDTCON<LVDSTAT> bit can be polled to determine if firmware can safely switch to
maximum frequency operation.
After the Power-up Timer expires and the microcontroller begins code execution, the
OSCTUNE<PLLEN> bit must be set by user firmware to activate the PLL (in
PLL-enabled modes). The PLL requires up to 2 ms to lock, during which time, the
microcontroller continues to execute code at the PLL-disabled frequency. User firm-
ware should not attempt to enable the USB module by setting the UCON<USBEN> bit
until after the PLL has locked (unless the PLL is not being used to derive the USB
module clock).
USB microcontrollers, such as the PIC18F4550, but the implementation of the surround-
ing clock structure is slightly different. When migrating up to the PIC18F87J50 family of
devices, the most important change is the PLL does not automatically start when the
microcontroller is powered on, even if it is programmed to use one of the PLL-enabled
modes (e.g., HS+PLL). This allows the microcontroller to start up at less than the
maximum operating frequency. This can potentially be advantageous when running from
a decaying power source (such as a battery), where the applied voltage may not be
adequate for maximum frequency operation. For applications such as these, the
WDTCON<LVDSTAT> bit can be polled to determine if firmware can safely switch to
maximum frequency operation.
After the Power-up Timer expires and the microcontroller begins code execution, the
OSCTUNE<PLLEN> bit must be set by user firmware to activate the PLL (in
PLL-enabled modes). The PLL requires up to 2 ms to lock, during which time, the
microcontroller continues to execute code at the PLL-disabled frequency. User firm-
ware should not attempt to enable the USB module by setting the UCON<USBEN> bit
until after the PLL has locked (unless the PLL is not being used to derive the USB
module clock).
2.4.3
Input Buffer Selection
The PIC18F87J50 family of microcontrollers offers more flexibility compared to
previous PIC18 devices when selecting which I/O pins should use analog input buffers,
and which ones should use digital input buffers. Previous PIC18 microcontrollers used
the ADCON1 register to control this function, but the PIC18F87J50 family devices use
two new registers, ANCON0 and ANCON1, for this purpose. These new registers allow
the PIC18F87J50 family of microcontrollers to individually and independently select
which ANx pins should use digital or analog input buffers. See the Analog-to-Digital
converter chapter in the device data sheet for more details.
previous PIC18 devices when selecting which I/O pins should use analog input buffers,
and which ones should use digital input buffers. Previous PIC18 microcontrollers used
the ADCON1 register to control this function, but the PIC18F87J50 family devices use
two new registers, ANCON0 and ANCON1, for this purpose. These new registers allow
the PIC18F87J50 family of microcontrollers to individually and independently select
which ANx pins should use digital or analog input buffers. See the Analog-to-Digital
converter chapter in the device data sheet for more details.