Microchip Technology DM164134 Scheda Tecnica
© 2006 Microchip Technology Inc.
DS41159E-page 165
PIC18FXX8
FIGURE 17-14:
I
2
C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SD
A
SC
L
S
SPI
F
B
F
(
S
S
PST
A
T
<0
>)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
1
1
1
1
0
A
9A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7D
6D
5
D
4
D
3
D
1
D
0
Re
ce
ive
Da
ta
B
y
te
AC
K
R/W
=
0
ACK
Receive F
irst B
y
te o
f A
ddre
s
s
C
lea
re
d i
n
s
o
ft
w
ar
e
D2
6
(P
IR
1<
3>
)
C
lea
re
d i
n
s
o
ft
w
ar
e
R
e
cei
v
e S
e
co
nd B
y
te of
A
d
d
ress
C
le
a
red
by har
dw
are
w
hen
S
S
P
A
D
D
i
s
upda
ted w
it
h
lo
w
b
y
te of
addr
ess afte
r falling
edge
UA
(
S
SPS
T
A
T
<
1
>
)
Clo
ck is h
e
ld
lo
w u
n
til
up
date o
f S
S
P
A
D
D
ha
s
ta
ken
pl
ace
U
A
i
s
set
in
di
cati
ng
that
th
e S
S
P
A
D
D
n
eeds to
be
u
pdate
d
UA
is se
t indicatin
g
that
S
S
P
A
D
D
nee
ds to b
e
upda
ted
C
lear
ed by h
a
rdw
a
re w
h
e
n
S
S
P
A
D
D
i
s
u
pdate
d
w
it
h hi
gh
byte
of ad
dress a
fter
fal
ling ed
ge
SSP
BUF is
wr
it
te
n
w
it
h
co
ntent
s o
f S
S
P
S
R
D
u
mm
y read
of S
S
P
B
U
F
to clear
B
F
flag
AC
K
CK
P
12
3
4
5
7
8
9
D7
D6
D
5
D4
D3
D1
D0
Re
ce
ive
Da
ta
Byte
B
u
s m
a
ster
term
inates
tran
sfer
D2
6
AC
K
C
le
a
red i
n
softw
ar
e
C
lea
re
d i
n
s
o
ft
w
a
re
SS
PO
V (
SSP
CO
N1
<6
>)
CK
P
written
to ‘
1
’
No
te
:
A
n
up
date
of th
e S
S
P
A
D
D
re
g
iste
r b
e
fo
re
t
h
e
fa
llin
g
ed
ge of
the n
inth cl
ock
w
ill
ha
ve no
ef
fect o
n
U
A
and
UA will
r
e
m
a
in
se
t.
No
te
:
A
n
up
date of the
S
S
P
A
D
D
re
g
is
ter
be
fo
re
t
h
e f
a
lli
n
g
e
dge
of the
ninth
clock will
h
a
ve n
o
ef
fect
on U
A
and
UA will r
e
m
a
in
se
t.
in softwar
e
Clo
ck is h
e
ld
l
o
w u
n
til
upda
te of S
S
P
A
D
D
has
ta
k
e
n
pl
ac
e
of n
inth cl
ock
o
f ni
nth
cl
ock
SS
PO
V is
s
e
t
be
cause S
S
P
B
U
F i
s
still fu
ll. ACK
i
s
not se
nt.
D
u
mmy r
ead
of S
S
P
B
U
F
to
clear
B
F
flag
Clo
ck is h
e
ld
lo
w u
n
ti
l
CK
P
is se
t to ‘
1
’
Clo
ck is n
o
t h
e
ld
lo
w
be
c
a
u
s
e A
C
K
=
1