Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
154
Freescale Semiconductor
2.4.3.9
Port T
This port is associated with LCD and TIM.
2.4.3.10
Port U
This port is associated with the Motor Driver/TIM0.
2.4.3.11
Port V
This port is associated with the Motor Driver/TIM1/SPI/IIC/PWM.
2.4.4
Pin interrupts
Ports T, S, R, AD offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (
) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (
and
).
Figure 2-95. Interrupt Glitch Filter on Port T,S,R, and AD(PPS=0)
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
t
pign
t
pval
uncertain