Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
181
Chapter 4
Interrupt (S12XINTV2)
Interrupt (S12XINTV2)
4.1
Introduction
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
•
I bit and X bit maskable interrupt requests
•
One non-maskable unimplemented op-code trap
•
One non-maskable software interrupt (SWI) or background debug mode request
•
One non-maskable system call interrupt (SYS)
•
Three non-maskable access violation interrupts
•
One spurious interrupt vector request
•
Three system reset vector requests
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
NOTE
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported. It is superseded by the 7-level interrupt request
priority scheme.
is no longer supported. It is superseded by the 7-level interrupt request
priority scheme.
Table 4-1. Revision History
Revision
Number
Revision Date
Sections
Affected
Description of Changes
V02.00
01 Jul 2005
Initial V2 release, added new features:
- XGATE threads can be interrupted.
- SYS instruction vector.
- Access violation interrupt vectors.
- XGATE threads can be interrupted.
- SYS instruction vector.
- Access violation interrupt vectors.
V02.04
11 Jan 2007
- Added Notes for devices without XGATE module.
V02.05
20 Mar 2007
- Fixed priority definition for software exceptions.
V02.07
13 Dec 2011
- Re-worded for difference of Wake-up feature between STOP and WAIT
modes.
modes.