Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

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DEMO9S12XHY256
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MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
199
Chapter 5
Background Debug Module (S12XBDMV2)
5.1
Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the
HCS12X core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
TAGGO command no longer supported by BDM
External instruction tagging feature now part of DBG module
BDM register map and register content extended/modified
Global page access functionality
Enabled but not active out of reset in emulation modes (if modes available)
CLKSW bit set out of reset in emulation modes (if modes available).
Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices
is 0xC1)
5.1.1
Features
The BDM includes these distinctive features:
Single-wire communication with host development system
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL command
Table 5-1. Revision History
Revision
Number
Revision Date
Sections
Affected
Description of Changes
V02.00
07 Mar 2006
- First version of S12XBDMV2
V02.01
14 May 2008
- Introduced standardized Revision History Table
V02.02
12 Sep 2012
- Minor formatting corrections