Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

Freescale Semiconductor

255

Referring to

. ADRH, ADRM, ADRL denote address high, middle and low byte respectively.

INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step.
The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst
tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0]
is incremented after each separate entry. In Detail mode DBGCNT[0] remains cleared whilst the other
DBGCNT bits are incremented on each trace buffer entry.

When a COF occurs a trace buffer entry is made and the corresponding CDV  bit is set.

Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL )
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte3 and the byte at the higher address is stored to byte2.

S12XCPU

Detail

CXINF1

CADRH1

CADRM1

CADRL1

CDATAH1

CDATAL1

CXINF2

CADRH2

CADRM2

CADRL2

CDATAH2

CDATAL2

CPU12X

Other Modes

CINF1

CPCH1

CPCM1

CPCL1

CINF0

CPCH0

CPCM0

CPCL0

CINF3

CPCH3

CPCM3

CPCL3

CINF2

CPCH2

CPCM2

CPCL2