Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

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Freescale Semiconductor

The clock generator creates the clocks used in the MCU (see

). The gating condition placed on

top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.

The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see

) Oscillator clock source is switched

to PLLCLK running at its minimum frequency f

SCM

. The Bus Clock is used to generate the clock visible

at the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus Clock.
But note that a CPU cycle corresponds to one Bus Clock.

IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned
off by clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a
maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks
freeze and CPU activity ceases.

OSCILLATOR

PHASE

LOCK

LOOP (IIPLL)

EXTAL

XTAL

SYSCLK

RTI

OSCCLK

PLLCLK

CLOCK PHASE

GENERATOR

Bus Clock

Clock

Monitor

1

0

PLLSEL or SCM

÷2

Core Clock

COP

Oscillator

= Clock Gate

WAIT(RTIWAI),

STOP(PSTP, PRE),

RTI ENABLE

WAIT(COPWAI),

STOP(PSTP, PCE),

COP ENABLE

STOP

1

0

SCM

Clock

STOP

STOP(PSTP),

LCD ENABLE

LCD Clock