Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
S12XE Clocks and Reset Generator (S12XECRGV2)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
287
7.5.1
Description of Reset Operation
The reset sequence is initiated by any of the following events:
•
Low level is detected at the RESET pin (External Reset).
•
Power on is detected.
•
Low voltage is detected.
•
Illegal Address Reset is detected (refer to device MMC information for details).
•
COP watchdog times out.
•
Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see
(see
). Since entry into reset is asynchronous it does not require a running SYSCLK. However,
the internal reset circuit of the S12XECRG cannot sequence out of current reset condition without a
running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional
SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the
RESET pin is released. The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and
then samples the RESET pin to determine the originating source.
running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional
SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the
RESET pin is released. The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and
then samples the RESET pin to determine the originating source.
shows which vector will be
fetched.
NOTE
External circuitry connected to the RESET pin should be able to raise the
signal to a valid logic one within 64 SYSCLK cycles after the low drive is
released by the MCU. If this requirement is not adhered to the reset source
will always be recognized as “External Reset” even if the reset was initially
caused by an other reset source.
signal to a valid logic one within 64 SYSCLK cycles after the low drive is
released by the MCU. If this requirement is not adhered to the reset source
will always be recognized as “External Reset” even if the reset was initially
caused by an other reset source.
COP Watchdog Reset
COPCTL (CR[2:0] nonzero)
Table 7-17. Reset Vector Selection
Sampled RESET Pin
(64 cycles after release)
Clock Monitor
Reset Pending
COP
Reset Pending
Vector Fetch
1
0
0
POR / LVR /
Illegal Address Reset/
External Reset
1
1
X
Clock Monitor Reset
1
0
1
COP Reset
0
X
X
POR / LVR /
Illegal Address Reset/ External Reset
with rise of RESET pin
Table 7-16. Reset Summary
Reset Source
Local Enable