Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

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Freescale Semiconductor

3. Shutdown mode

Controlled by VREGEN (see device level specification for connectivity of VREGEN).

This mode is characterized by minimum power consumption. The regulator outputs are in a
high-impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The
API internal RC oscillator clock is not available.

This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the
VREG_3V3 to use external supplies.

shows the function principle of VREG_3V3 by means of a block diagram. The regulator core

REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output
voltages.