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Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

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Voltage Regulator (S12VREGL3V3V1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
300
Freescale Semiconductor
9.3.1
Module Memory Map
A summary of the registers associated with the VREG_3V3 sub-block is shown in
. Detailed
descriptions of the registers and bits are given in the subsections that follow
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x02F0
VREGHTCL
R
0
0
VSEL
VAE
HTEN
HTDS
HTIE
HTIF
W
0x02F1
VREGCTRL
R
0
0
0
0
0
LVDS
LVIE
LVIF
W
0x02F2
VREGAPIC
L
R
APICLK
0
0
APIFES
APIEA
APIFE
APIE
APIF
W
0x02F3
VREGAPIT
R
R
APITR5
APITR4
APITR3
APITR2
APITR1
APITR0
0
0
W
0x02F4
VREGAPIR
H
R
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
W
0x02F5
VREGAPIR
L
R
APIR7
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
W
0x02F6
Reserved
06
R
0
0
0
0
0
0
0
0
W
0x02F7
VREGHTTR
R
HTOEN
0
0
0
HTTR3
HTTR2
HTTR1
HTTR0
W
Table 9-3. Register Summary