Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
Voltage Regulator (S12VREGL3V3V1)
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
307
9.3.2.6
Reserved 06
The Reserved 06 is reserved for test purposes.
9.3.2.7
High Temperature Trimming Register (VREGHTTR)
The VREGHTTR register allows to trim the VREG temperature sense.
Fiption
Table 9-12. Trimming Effect
0x02F6
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-7. Reserved 06
0x02F7
7
6
5
4
3
2
1
0
R
HTOEN
0
0
0
HTTR3
HTTR2
HTTR1
HTTR0
W
Reset
0
0
0
0
0
1
0
1
0
1
0
1
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
= Unimplemented or Reserved
Figure 9-8. VREGHTTR
Table 9-11. VREGHTTR field descriptions
Field
Description
7
HTOEN
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
3–0
HTTR[3:0]
High Temperature Trimming Bits — See
for trimming effects.
Bit
Trimming Effect
HTTR[3]
Increases V
HT
twice of HTTR[2]
HTTR[2]
Increases V
HT
twice of HTTR[1]
HTTR[1]
Increases V
HT
twice of HTTR[0]
HTTR[0]
Increases V
HT
(to compensate Temperature Offset)