Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
Codici prodotto
DEMO9S12XHY256
Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
367
Read:
•
For transmit buffers, anytime when TXEx flag is set (see
”) and the corresponding transmit buffer is selected in CANTBSEL (see
”).
•
For receive buffers, only when RXF flag is set (see
Write:
•
For transmit buffers, anytime when TXEx flag is set (see
”) and the corresponding transmit buffer is selected in CANTBSEL (see
”).
•
Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation
11.3.3.1
Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE,
and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
= Unused, always read ‘x’
Figure 11-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
IDR0
0x00X0
R
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
W
IDR1
0x00X1
R
ID2
ID1
ID0
RTR
IDE (=0)
W
IDR2
0x00X2
R
W
IDR3
0x00X3
R
W
= Unused, always read ‘x’
Figure 11-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Register
Name
Bit 7
6
5
4
3
2
1
Bit0