Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
Inter-Integrated Circuit (IICV3) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
397
12.3.1.1
IIC Address Register (IBAD)
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
the address sent on the bus during the address transfer.
12.3.1.2
IIC Frequency Divider Register (IBFD)
Read and write anytime
Module Base +0x0000
7
6
5
4
3
2
1
0
R
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-3. IIC Bus Address Register (IBAD)
Table 12-2. IBAD Field Descriptions
Field
Description
7:1
ADR[7:1]
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
mode of IIC bus is slave mode for an address match on the bus.
0
Reserved
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-4. IIC Bus Frequency Divider Register (IBFD)
Table 12-3. IBFD Field Descriptions
Field
Description
7:0
IBC[7:0]
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in