Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
Inter-Integrated Circuit (IICV3) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
409
Figure 12-10. IIC-Bus Transmission Signals
12.4.1.1
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in
high), a master may initiate communication by sending a START signal.As shown in
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
Figure 12-11. Start and Stop Conditions
CL
DA
Start
Signal
Ack
Bit
1
2
3
4
5
6
7
8
MSB
LSB
1
2
3
4
5
6
7
8
MSB
LSB
No
CL
DA
1
2
3
4
5
6
7
8
MSB
LSB
1
2
5
6
7
8
MSB
LSB
Repeated
3
4
9
9
ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Calling Address
Read/
Data Byte
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W
New Calling Address
9
9
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address
Read/
Write
No
Ack
Bit
Read/
Write
SDA
SCL
START Condition
STOP Condition