Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

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To calculate the output frequency in center aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period
register for that channel.

•

PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)

•

PWMx Duty Cycle (high time as a% of period):

— Polarity = 0 (PPOLx = 0)

Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

— Polarity = 1 (PPOLx = 1)

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

As an example of a center aligned output, consider the following case:

Clock Source = E, where E = 10 MHz (100 ns period)

PPOLx = 0

PWMPERx = 4

PWMDTYx = 1

PWMx Frequency = 10 MHz/8 = 1.25 MHz

PWMx Period = 800 ns

PWMx Duty Cycle = 3/4 *100% = 75%

Shown in

 is the output waveform generated.

The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater
PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.

The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and
5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and
channels 0 and 1 are concatenated with the CON01 bit.

Change these bits only when both corresponding channels are disabled.

When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double
byte channel, as shown in

. Similarly, when channels 4 and 5 are concatenated, channel 4

registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated,

E = 100 ns

DUTY CYCLE = 75%

E = 100 ns

PERIOD = 800 ns