Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

Freescale Semiconductor

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The pulse accumulator counter can operate in event counter mode even
when the timer enable bit, TEN, is clear.

Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active
level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE
bit selects low levels or high levels to enable the divided-by-64 clock.

The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to
generate interrupt requests.

The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the
last reset.

The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.

The reset state of each individual bit is listed within

which details the registers and their bit fields.

This section describes interrupts originated by the TIM16B8CV2 block.

 lists the interrupts

generated by the TIM16B8CV2 to communicate with the MCU.

The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.

1

Chip Dependent.

C[7:0]F

—

—

—

Timer Channel 7–0

Active high timer channel interrupts 7–0

PAOVI

—

—

—

Pulse Accumulator

Input

Active high pulse accumulator input interrupt

PAOVF

—

—

—

Pulse Accumulator

Overflow

Pulse accumulator overflow interrupt

TOF

—

—

—

Timer Overflow

Timer Overflow interrupt