Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

550

Freescale Semiconductor

This section consists of register descriptions. Each description includes a standard register diagram.
Details of register bit and field function follow the register diagrams, in bit order.

Read: anytime

Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty

select bits must not be changed when the LCD is enabled.

Module Base + 0x0000

7

6

5

4

3

2

1

0

R

LCDEN

0

LCLK2

LCLK1

LCLK0

BIAS

DUTY1

DUTY0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

7

LCDEN

LCD40F4BV2 Driver System Enable — The LCDEN bit starts the LCD waveform generator.
0 All frontplane and backplane pins are disabled. In addition, the LCD40F4BV2 system is disabled

and all LCD waveform generation clocks are stopped.

1 LCD driver system is enabled. All FP[39:0] pins with FP[39:0]EN set, will output an LCD driver

waveform The BP[3:0] pins will output an LCD40F4BV2 driver waveform based on the settings of DUTY0
and DUTY1.

5:3

LCLK[2:0]

LCD Clock Prescaler — The LCD clock prescaler bits determine the IRCCLK divider value to produce the LCD
clock frequency. For detailed description of the correlation between LCD clock prescaler bits and the divider
value please refer to

.

2

BIAS

BIAS Voltage Level Select — This bit selects the bias voltage levels during various LCD operating modes, as
shown in

.

1:0

DUTY[1:0]

LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD40F4BV2 driver
system, as shown in