Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

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DEMO9S12XHY256

Device Overview MC9S12XHY-Family

MC9S12XHY-Family Reference Manual, Rev. 1.04

Freescale Semiconductor

1.11.2

Vectors

Table 1-11

lists all interrupt sources and vectors in the default order of priority. The interrupt module (see

Section Chapter 4 Interrupt (S12XINTV2)) provides an interrupt vector base register (IVBR) to
relocate the vectors.

Table 1-11. Interrupt Vector Locations (Sheet 1 of 4)

Vector Address

(1)

Interrupt Source

CCR

Mask

Local Enable

Stop

wakeup

Wait

wakeup

Vector base + $F8

Unimplemented instruction trap

None

Vector base+ $F6

SWI

None

Vector base+ $F4

XIRQ

X Bit

IRQCR

(XIRQEN)

yes

Vector base+ $F2

IRQ

I bit

IRQCR (IRQEN)

yes

Vector base+ $F0

Real time interrupt

I bit

CRGINT (RTIE)

yes

Vector base+ $EE

TIM0 timer channel 0

I bit

TIM0TIE (C0I)

yes

Vector base + $EC

TIM0 timer channel 1

I bit

TIM0TIE (C1I)

yes

Vector base+ $EA

TIM0 timer channel 2

I bit

TIM0TIE (C2I)

yes

Vector base+ $E8

TIM0 timer channel 3

I bit

TIM0TIE (C3I)

yes

Vector base+ $E6

TIM0 timer channel 4

I bit

TIM0TIE (C4I)

yes

Vector base + $E4

TIM0 timer channel 5

I bit

TIM0TIE (C5I)

yes

Vector base+ $E2

TIM0 timer channel 6

I bit

TIM0TIE (C6I)

yes

Vector base+ $E0

TIM0 timer channel 7

I bit

TIM0TIE (C7I)

yes

Vector base+ $DE

TIM0 timer overflow

I bit

TIM0TSRC2

(TOF)

yes

Vector base+ $DC

TIM0 Pulse accumulator A overflow

I bit

TIM0PACTL

(PAOVI)

yes

Vector base + $DA

TIM0 Pulse accumulator input edge

I bit

TIM0PACTL

(PAI)

yes

Vector base + $D8

SPI

I bit

SPICR1 (SPIE,

SPTIE)

yes

Vector base+ $D6

SCI0

I bit

SCI0CR2

(TIE, TCIE, RIE,

ILIE)

yes

Vector base + $D4

SCI1

I bit

SCI1CR2

(TIE, TCIE, RIE,

ILIE)

yes

Vector base + $D2

ATD

I bit

ATDCTL2

(ASCIE)

yes

Vector base + $D0

Reserved

Vector base + $CE

Port AD

I bit

PIEAD

(PIEAD7-

PIEAD0)

yes