Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente
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DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
66
Freescale Semiconductor
2.1
Introduction
2.1.1
Overview
The S12XHY Family Port Integration Module establishes the interface between the peripheral modules
and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers:
•
Port A associated with the XLKS,IRQ, XIRQ interrupt inputs and API_EXTCLK. Also associated
with the LCD driver output
with the LCD driver output
•
Port B used as general purpose I/O and LCD driver output(including BP and FP pins)
•
Port R associated with 2 timer module - port 4:0 inputs can be used as an external interrupt
source.Also associated with the LCD driver output. PR also associated with the IIC and CAN1
source.Also associated with the LCD driver output. PR also associated with the IIC and CAN1
•
Port T associated with 2 timer module. Also associated with the LCD driver output. It can be used
as external interrupt source
as external interrupt source
•
Port S associated with 1 SPI module, 1 SCI module, 1 IIC module and 1 MSCAN, and PWM. Port
6-5and 3-2 can be used as an external interrupt source.
6-5and 3-2 can be used as an external interrupt source.
•
Port P connected to the PWM, also associated with LCD driver output
•
Port H associated with 1 SPI, 1 SCI. Also associated with LCD driver output
•
Port M associated with SCI1 PWM and TIM
•
Port AD associated with one 12-channel ATD module. It an be used as an external interrupt source
•
Port U/V associated with the Motor driver output. Also PV3-0 associated with 1 SPI, 1 IIC and 4
PWM channels. PU0/PU2/PU4/PU6 and PV0/PV2/PV4/PV6 associated with TIM0 channels 0 -3
and TIM1 channels 0 -3
PWM channels. PU0/PU2/PU4/PU6 and PV0/PV2/PV4/PV6 associated with TIM0 channels 0 -3
and TIM1 channels 0 -3
Most I/O pins can be configured by register bits to select data direction, to enable and select pull-up or
pull-down devices. Port U/V have register bits to select the slew rate control.
pull-down devices. Port U/V have register bits to select the slew rate control.
NOTE
This document assumes the availability of all features (112-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary section.
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary section.
0.11
15 Nov
2010
add NCLKX2 bit on ECLKCTL register
fix typo,it is PTIM and PTM
remove Reduced drive at section 2.4.2.4 and
fix table
, PM[1:0] is for TXD/RXD
fix table
0.12
1 Nov
2012
fix typo of unit at
,
Version
Number
Revision
Date
Effective
Date
Author
Description of Changes