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Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manuale Utente

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Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
95
2.3.16
Port T Data Direction Register (DDRT)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTT or PTIT registers, when changing the
DDRT register.
2.3.17
PIM Reserved Register
 Address 0x0242
Access: User read/write
1
1
Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-14. Port T Data Direction Register (DDRT)
Table 2-13. DDRT Register Field Descriptions
Field
Description
7-4
DDRT
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding TIM0 output compare channel is enabled, it will be forced as output.
1 Associated pin is configured as output
0 Associated pin is configured as input
3-0
DDRT
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding TIM1 output compare channel is enabled, it will be forced as output.
1 Associated pin is configured as output
0 Associated pin is configured as input
 Address 0x0243
Access: User read/write
1
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
W
Reset
0
0
0
0
0
0
0
0
Figure 2-15. PIM Reserved Register