Redpitaya RED PITAYA, OPEN SOURCE LAB RED Pitaya V 1.1 Scheda Tecnica
Codici prodotto
RED Pitaya V 1.1
32
redpitaya> monitor -ams
#ID
#ID
Desc
Raw
Val
0
Temp(0C-85C) a4f
51.634
1
AI0(0-3.5V) 1
0.002
2
AI1(0-3.5V) 13
0.033
3
AI2(0-3.5V) 1
0.002
4
AI3(0-3.5V) 2
0.003
5
AI4(5V0)
669
4.898
6
VCCPINT(1V0) 55c
1.005
7
VCCPAUX(1V8) 9a9
1.812
8
VCCBRAM(1V0) 55d
1.006
9
VCCINT(1V0) 55b
1.004
10
VCCAUX(1V8) 9ab
1.813
11
VCCDDR(1V5) 809
1.507
12
AO0(0-1.8V) 2b0000 0.496
13
AO1(0-1.8V) 150000 0.242
14
AO2(0-1.8V) 2b0000 0.496
15
AO3(0-1.8V) 220000 0.392
The –ams switch provides access to analog mixed signals including Zynq SoC temperature,
auxiliary analog input reading, power supply voltages and configured auxiliary analog output
settings. The auxiliary analog outputs can be set through the monitor utility:
auxiliary analog input reading, power supply voltages and configured auxiliary analog output
settings. The auxiliary analog outputs can be set through the monitor utility:
redpitaya> monitor -sdac 0.9 0.8 0.7 0.6
6.1.6 Accessing FPGA registers
Red Pitaya signal processing is based on two computational engines: the FPGA and the dual core
processor in order to effectively split the tasks. Most of the high data rate signal processing is
implemented within the FPGA building blocks. These blocks can be configured parametrically
through registers. The FPGA registers are documented in the “RedPitaya_HDL_memory_map-xxx”
document. The registers can be accessed using the described monitor utility. For example, the
following sequence of monitor commands checks, modifies and verifies the acquisition decimation
parameter (at address 0x40100014):
processor in order to effectively split the tasks. Most of the high data rate signal processing is
implemented within the FPGA building blocks. These blocks can be configured parametrically
through registers. The FPGA registers are documented in the “RedPitaya_HDL_memory_map-xxx”
document. The registers can be accessed using the described monitor utility. For example, the
following sequence of monitor commands checks, modifies and verifies the acquisition decimation
parameter (at address 0x40100014):
redpitaya> monitor 0x40100014
0x00000001
redpitaya>
redpitaya> monitor 0x40100014 0x8
redpitaya> monitor 0x40100014
0x00000008
redpitaya>
0x00000001
redpitaya>
redpitaya> monitor 0x40100014 0x8
redpitaya> monitor 0x40100014
0x00000008
redpitaya>
Note: The CPU algorithms communicate with FPGA through these registers. Therefore,
the user should be aware of a possible interference with Red Pitaya applications, reading
or acting upon these same FPGA registers. For simple tasks, however, the monitor utility
can be used by high level scripts (Bash, Python, Matlab...) to communicate directly with
FPGA if necessary.
the user should be aware of a possible interference with Red Pitaya applications, reading
or acting upon these same FPGA registers. For simple tasks, however, the monitor utility
can be used by high level scripts (Bash, Python, Matlab...) to communicate directly with
FPGA if necessary.