Infineon DDR2 2GB 667MHz CL5 AET861FB00-30D Scheda Tecnica

 

AENEON™ Data Sheet

5

Revision 1.10, 2008-05

A Qimonda AG Brand

Doc. # 12272007-OKYD-PLKJ

DDR2 Fully Buffered

Memory Module

The information herein is given to describe certain components and shall not be

considered as a guarantee of characteristics. Terms of delivery and rights to

technical change reserved. We hereby disclaim any and all warranties, including

but not limited to warranties of non-infringement, regarding circuits,

descriptions, and charts stated herein.

Due to technical requirements components may contain dangerous substances.

For information on the types in question please contact your nearest distribution

partner.

Components may only be used in life support devices or systems with the

express written approval of Qimonda AG, if a failure of such components can

reasonably be expected to cause the failure of that life support device or system,

or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to

support and/or maintain and sustain and/or protect human life. If they fail, it is

reasonable to assume that the health of the user or other persons may be

endangered.

To obtain more information about these products, please contact your AENEON representative.

5) Measured delay at FB-DIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 

0 (connector pins 142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector 
pins 22 & 23).

6) Measured delay at FB-DIMM gold finger between the center of the1st UI of command frame on the primary southbound 

lane 81 (connector pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 
(connector pins 22 & 23) – [CL (DRAM CAS latency) value] * [frame clock period – AL (DRAM additional latency) value 
* frame clock period].