Samsung RAM DDR2 2GB, PC800 M378T5663DZ3-CF7 Dépliant

Used component part #

:K4T1G084QD-ZCF7

# of banks in component

:8 banks

Bin Sort : F7(DDR2-800@CL=6)

0

# of Serial PD Bytes written during module production

1

128bytes

80h

1

Total Number of SPD memory device

2

256bytes(2k bit)

08h

2

Fundameatal memory type

DDR2 SDRAM

08h

3

# of row address on this assembly

14

0Eh

4

# of column address on this assembly

10

0Ah

5

# of module rows on this assembly

2 Row, Planar, 30.0mm

61h

6

Data width of this assembly

64bits

40h

7

Reserved

-

00h

8

Voltage interface level of this assembly

SSTL 1.8V

05h

9

DDR2 SDRAM cycle time at Max. Supported CAS latency=X

3

2.5ns

25h

10

DDR2 SDRAM Access time from clock at CL=X

+/-0.40ns

40h

11

DIMM configuration type (address&command parity, data parity,
ECC)

Non parity/ECC

00h

12

Refresh rate

3,4

7.8us

82h

13

Primary DDR2 SDRAM width

x8

08h

14

Error checking DDR2 SDRAM data width

N/A

00h

15

Reserved

-

00h

16

DDR2 SDRAM device attributes : Burst lengths supported

4,8

0Ch

17

DDR2 SDRAM device attributes : # of banks on each DDR2 SDRAM
device

3

8 banks

08h

18

DDR2 SDRAM device attributes : CAS latency supported

6,5,4

70h

19

DIMM Mechanical Characteristics

X =< 4.10

01h

20

DIMM type information

3

Regular UDIMM

02h

21

DDR2 SDRAM module attributes

Analysis probe not installed, FET switch
external not enable

00h

22

DDR2 SDRAM device attributes : General

Supports weak driver, 50Ohm ODT, PASR

07h

23

DDR2 SDRAM cycle time at CL= X-1

3.0ns

30h

24

DDR2 SDRAM access time from clock at CL= X-1

+/- 0.45ns

45h

25

DDR2 SDRAM cycle time at CL= X-2

3.75ns

3Dh

26

DDR2 SDRAM access time from clock at CL= X-2

+/-0.5ns

50h

27

Minimum row precharge time(=tRP)

15ns

3Ch

28

Minimum row active to row active delay(=tRRD)

3

7.5ns

1Eh

29

Minimum RAS to CAS delay(=tRCD)

15ns

3Ch

30

Minimum active  precharge time(=tRAS)  

45ns

2Dh

31

Module rank density

1GB

01h

32

Command and address setup time before clock(=tIS)

3

0.17ns

17h

33

Command and address hold time after clock(=tIH)

3

0.25ns

25h

34

Data input setup time before strobe(=tDS)

3

0.05ns

05h

35

Data input hold time after strobe(=tDH)

3

0.12ns

12h

36

Write recovery time(=tWR)

3

15ns

3Ch

37

Internal write to read command delay(=tWTR)

3

7.5ns

1Eh

38

Internal read to precharge command delay(=tRTP)

3

7.5ns

1Eh

39

Memory analysis probe characteristics

-

00h