Analog Devices AD9609 Evaluation Board AD9609-65EBZ AD9609-65EBZ Scheda Tecnica
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AD9609-65EBZ
AD9609
Rev. 0 | Page 9 of 32
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
AVDD to AGND
−0.3 V to +2.0 V
DRVDD to AGND
−0.3 V to +3.9 V
VIN+, VIN− to AGND
−0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND
−0.3 V to AVDD + 0.2 V
VREF to AGND
−0.3 V to AVDD + 0.2 V
SENSE to AGND
−0.3 V to AVDD + 0.2 V
VCM to AGND
−0.3 V to AVDD + 0.2 V
RBIAS to AGND
−0.3 V to AVDD + 0.2 V
CSB to AGND
−0.3 V to DRVDD + 0.3 V
SCLK/DFS to AGND
−0.3 V to DRVDD + 0.3 V
SDIO/PDWN to AGND
−0.3 V to DRVDD + 0.3 V
MODE/OR to AGND
−0.3 V to DRVDD + 0.3 V
D0 through D9 to AGND
−0.3 V to DRVDD + 0.3 V
DCO to AGND
−0.3 V to DRVDD + 0.3 V
Operating Temperature Range (Ambient)
−40°C to +85°C
Maximum Junction Temperature Under Bias
150°C
Storage Temperature Range (Ambient)
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle is the only ground connection for the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.
Table 7. Thermal Resistance
Package
Type
Type
Airflow
Velocity
(m/sec)
Velocity
(m/sec)
θ
θ
θ
Ψ
Unit
32-Lead LFCSP
5 mm × 5 mm
5 mm × 5 mm
0 37.1
3.1
20.7
0.3
°C/W
1.0 32.4
0.5
°C/W
2.5 29.1
0.8
°C/W
1
Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
Typical θ
JA
is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θ
which reduces θ
JA
. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θ
power planes, reduces the θ
JA
.
ESD CAUTION