Analog Devices AD9641 Evaluation Board AD9641-80KITZ AD9641-80KITZ Scheda Tecnica
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AD9641-80KITZ
Evaluation Board User Guide
UG-294
Rev. B | Page 13 of 48
Troubleshooting Tips
If the FFT plot appears abnormal, use the following trouble-
shooting tips:
• If you see a normal noise floor when you disconnect the
• If you see a normal noise floor when you disconnect the
signal generator from the analog input, be sure you are not
overdriving the ADC. Reduce the input level, if necessary.
overdriving the ADC. Reduce the input level, if necessary.
• In the VisualAnalog main window, click the Settings
button in the Input Formatter box. Check that Number
Format is set to the correct encoding (offset binary by
default). Repeat this procedure for the other channel.
Format is set to the correct encoding (offset binary by
default). Repeat this procedure for the other channel.
If the FFT appears normal but the performance is poor, use the
following troubleshooting tips:
• Ensure that an appropriate filter is used on the analog input.
• Check that the signal generators for the clock and the analog
• Ensure that an appropriate filter is used on the analog input.
• Check that the signal generators for the clock and the analog
input have low phase noise.
• Change the analog input frequency slightly if noncoherent
sampling is being used.
• Verify that the SPI configuration file matches the product
being evaluated.
If the FFT window remains blank after Run is clicked, use the
following troubleshooting tips:
• Check that the evaluation board is securely connected to
• Check that the evaluation board is securely connected to
the FIFO-GX board.
• Ensure that the FPGA has been programmed by verifying that
the DONE LED is illuminated on the FIFO-GX board. If
this LED is not illuminated, make sure the U4 switch on
the board is in the correct position for the USB
configuration.
this LED is not illuminated, make sure the U4 switch on
the board is in the correct position for the USB
configuration.
• Verify that the correct FPGA program was installed by
clicking the Settings button in the ADC Data Capture box in
VisualAnalog, and then clicking the FPGA tab and verifying
that the proper FPGA bin file is selected for the part.
VisualAnalog, and then clicking the FPGA tab and verifying
that the proper FPGA bin file is selected for the part.
If VisualAnalog indicates that the FIFO Capture timed out,
use the following troubleshooting tips:
• Ensure that all power and USB connections are secure.
• Probe the DCOA signal at RN801 (Pin 2) on the evaluation
• Ensure that all power and USB connections are secure.
• Probe the DCOA signal at RN801 (Pin 2) on the evaluation
board and confirm that a clock signal is present at the
ADC sampling rate.
ADC sampling rate.